VERILOG AND MODEL SIM SIMULATION

Hard ware descriptive language library for FPGA and synopsis synthesis for VLSI applications.

16 BIT ADDER

Adder module and test bench

DDER MODULE AND TEST BENCH

16bit adder.JPG

counter.JPG

Counter Implementation

Module and Test bench file

Counter 4 bits.JPG

16bit adder.JPG

This particular module has majorly all logic functions like and, or not, xor...........

The instance can be changed as required.

Download the files from github using the button below.

Module and Test Bench verilog files

Counter 4 bits.JPG

output.JPG

16bit adder.JPG

and.JPG

orgate.JPG

counter.JPG

dflipflop.JPG

Verilog and Modelsim: Research