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+1-6072806407
Masters in Biomedical Engineer
Cornell University
New York
VERILOG AND MODEL SIM SIMULATION
Hard ware descriptive language library for FPGA and synopsis synthesis for VLSI applications.
16 BIT ADDER
Adder module and test bench
16bit adder.JPG
counter.JPG
4 BIT UP COUNTER
Counter Implementation
Counter 4 bits.JPG
16bit adder.JPG
BASIC LOGIC FUNCTIONS AND MODEL SIM SETUP
This particular module has majorly all logic functions like and, or not, xor...........
The instance can be changed as required.
Download the files from github using the button below.
Counter 4 bits.JPG
output.JPG
16bit adder.JPG
and.JPG
orgate.JPG
counter.JPG
dflipflop.JPG
Verilog and Modelsim: Research
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