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VERILOG AND MODEL SIM SIMULATION







Hard ware descriptive language library for FPGA and synopsis synthesis for VLSI applications.

16 BIT ADDER

Adder module and test bench

DDER MODULE AND TEST BENCH

4 BIT UP COUNTER

Counter  Implementation

Module and Test bench file

BASIC LOGIC FUNCTIONS AND MODEL SIM SETUP

This particular module has majorly all logic functions like and, or not, xor...........


The instance can be changed as required.


Download the files from github using the button below.



Module and Test Bench verilog files
Verilog and Modelsim: Research
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