top of page
Search
  • Writer's pictureNavneet Singh

PSOC - Programable System on CHIP (Cypress)

Psocs : An island for Re Programmable Analog design


PSOC KIT Hardware Architecture :




History[edit]

In 2002, Cypress began shipping commercial quantities of the PSoC 1.[1] To promote the PSoC, Cypress sponsored a "PSoC Design Challenge" in Circuit Cellar magazine in 2002 and 2004.[2]

In April 2013, Cypress released the fourth generation, PSoC 4. The PSoC 4 features a 32-bit ARM Cortex-M0 CPU, with programmable analog blocks (operational amplifiers and comparators), programmable digital blocks (PLD-based UDBs), programmable routing and flexible GPIO (route any function to any pin), a serial communication block (for SPI, UART, I²C), a timer/counter/PWM block and more.[3]

PSoC is used in devices as simple as Sonicare toothbrushes and Adidas sneakers, and as complex as the TiVo set-top box. One PSoC, using CapSense, controls the touch-sensitive scroll wheel on the Apple iPod click wheel.

In 2014, Cypress extended the PSoC 4 family by integrating a Bluetooth Low Energy radio along with a PSoC 4 Cortex-M0-based SoC in a single, monolithic die.

In 2016, Cypress released PSoC 4 S-Series, featuring ARM Cortex-M0+ CPU.[4]

Overview[edit]

A PSoC integrated circuit is composed of a core, configurable analog and digital blocks, and programmable routing and interconnect. The configurable blocks in a PSoC are the biggest difference from other microcontrollers.

PSoC has three separate memory spaces: paged SRAM for data, Flash memory for instructions and fixed data, and I/O registers for controlling and accessing the configurable logic blocks and functions. The device is created using SONOS technology.

PSoC resembles an ASIC: blocks can be assigned a wide range of functions and interconnected on-chip. Unlike an ASIC, there is no special manufacturing process required to create the custom configuration — only startup code that is created by Cypress' PSoC Designer (for PSoC 1) or PSoC Creator (for PSoC 3 / 4 / 5) IDE.

PSoC resembles an FPGA in that at power up it must be configured, but this configuration occurs by loading instructions from the built-in Flash memory.

PSoC most closely resembles a microcontroller combined with a PLD and programmable analog. Code is executed to interact with the user-specified peripheral functions (called "Components"), using automatically generated APIs and interrupt routines. PSoC Designer or PSoC Creator generate the startup configuration code. Both integrate APIs that initialize the user selected components upon the users needs in a Visual-Studio-like GUI.

Configurable analog and digital blocks[edit]

PsoC Block Example

Using configurable analog and digital blocks, designers can create and change mixed-signal embedded applications. The digital blocks are state machines that are configured using the blocks registers. There are two types of digital blocks, Digital Building Blocks (DBBxx) and Digital Communication Blocks (DCBxx). Only the communication blocks can contain serial I/O user modules, such as SPI, UART, etc.

Each digital block is considered an 8-bit resource that designers can configure using pre-built digital functions or user modules (UM), or, by combining blocks, turn them into 16-, 24-, or 32-bit resources. Concatenating UMs together is how 16-bit PWMs and timers are created.

There are two types of analog blocks. The continuous time (CT) blocks are composed of an op-amp circuit and designated as ACBxx where xx is 00–03. The other type is the switch cap (SC) blocks, which allow complex analog signal flows and are designated by ASCxy where x is the row and y is the column of the analog block. Designers can modify and personalize each module to any design.

Programmable routing and interconnect[edit]

PSoC mixed-signal arrays' flexible routing allows designers to route signals to and from I/O pins more freely than with many competing microcontrollers. Global buses allow for signal multiplexing and for performing logic operations. Cypress suggests that this allows designers to configure a design and make improvements more easily and faster and with fewer PCB redesigns than a digital logic gate approach or competing microcontrollers with more fixed function pins.

Series[edit]

There are five different families of devices, each based around a different microcontroller core:

  • PSoC 1 — CY8C2xxxx series — M8C core.

  • PSoC 3 — CY8C3xxxx series — 8051 core.

  • PSoC 4 — CY8C4xxxx series — ARM Cortex-M0 core.[5]

  • PSoC 5/5LP — CY8C5xxxx series — ARM Cortex-M3 core.

  • PSoC 6 — CY8C6xxxx series — ARM Cortex-M4 core with an added ARM Cortex-M0+ core (in some models).[6]

Bluetooth Low Energy

Starting in 2014, Cypress began offering PSoC 4 BLE devices with integrated Bluetooth Low Energy (Bluetooth Smart). This can be used to create connected products leveraging the analog and digital blocks.[7] Users can add and configure the BLE module directly in PSoC creator. Cypress also provides a complete Bluetooth Low Energy stack licensed from Mindtree with both Peripheral and Central functionality.[8] The PSoC 6 series includes versions with BLE including Bluetooth 5 features including extended range or higher speed.

Summary[edit]

PSoC 1PSoC 3PSoC 4PSoC 5/5LPPSoC 68-bit M8C core

up to 24 MHz, 4 MIPS8-bit 8051 core (single-cycle)

up to 67 MHz, 33 MIPS32-bit ARM Cortex-M0

up to 48 MHz, ? MIPS32-bit ARM Cortex-M3

up to 80 MHz, 84 MIPS32-bit ARM Cortex-M4 (up to 150 MHz)

32-bit ARM Cortex-M0+ (opt. up to 100 MHz)Flash: 4 KB to 32 KB

SRAM: 256 bytes to 2 KBFlash: 8 KB to 64 KB

SRAM: 3 KB to 8 KBFlash: 16 KB to 256 KB

SRAM: 2 KB to 32 KBFlash: 32 KB to 256 KB

SRAM: 8 KB to 64 KBFlash: 512 KB to 2048 KB

SRAM: 128 KB to 512 KB

expandable using quad SPII²C, SPI, UART,

FS USB 2.0I²C, SPI, UART, LIN,

FS USB 2.0, I²S, CANI²C, SPI, UART, CAN

.I²C, SPI, UART, LIN, CAN,

FS USB 2.0, I²S

I²C, SPI, UART, LIN, BLE (opt.), FS USB 2.0 (opt. host & device)16 digital PSoC blocks16 to 24 UDBs (Universal Digital Blocks)4 to 8 UDBs20 to 24 UDBs0 to 12 UDBs1 Delta-Sigma ADC (6 to 14-bit)

131 ksps @ 8-bit;

1 Sigma-Delta ADC (for capacitive sensing)

Up to two DACs (6 to 8-bit)

1 Delta-Sigma ADC (8 to 20-bit)

192 ksps @ 12-bit;

Up to four DACs (8-bit)

1 SAR ADC (12-bit)

1 Msps @ 12-bit;

Up to two DACs (7 to 8-bit)

1 Delta-Sigma ADC (8 to 20-bit)

192 ksps @12-bit;

2 SAR ADCs (12-bit)

1 Msps @ 12-bit;

Up to four DACs (8-bit)

1 SAR ADC (12-bit) 1 MSPS

1 12 Bit Voltage Mode DAC

Up to 64 I/OUp to 72 I/OUp to 98 I/OUp to 72 I/OUp to 104 I/OOperation: 1.7 V to 5.25 V

Active: 2 mA,

Sleep: 3 μA

Hibernate: ?Operation: 0.5 V to 5.5 V

Active: 1.2 mA,

Sleep: 1 μA,

Hibernate: 200 nAOperation: 1.71 V to 5.5 V

Active: 1.6 mA,

Sleep: 1.3 μA,

Hibernate: 150 nAOperation: 2.7 V to 5.5 V

Active: 2 mA,

Sleep: 2 μA,

Hibernate: 300 nARequires ICE Cube and FlexPodsOn-chip SWD, DebugOn-chip JTAG, SWD, SWV,

Debug, TraceCY8CKIT-001 Development KitCY8CKIT-001 Development Kit

CY8CKIT-

12 views0 comments

Recent Posts

See All

留言


Post: Blog2_Post
bottom of page